Example embodiments relate to a non-volatile memory device, and more particularly, to a non-volatile memory device and a method of programming the same.
A non-volatile memory device, for example a mask read-only memory (MROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc., may retain its stored data even if there is no power supply. The data stored state of a non-volatile memory may be permanent or reprogrammable according to applicable manufacturing techniques. A non-volatile memory device may be used for storing programs and microcodes in a wide range of applications, for example computers, avionics, communications, and consumer electronic technology industries. If a system requires a non-volatile memory that is reprogrammable and is capable of promptly combining of volatile and non-volatile memory storing modes in a single chip, a non-volatile RAM (nvRAM) may be used for the system. Moreover, a certain memory structure with additional logic circuits has been developed and may optimize performance for an application oriented task.
With non-volatile semiconductor memory devices like MROM, PROM, and EPROM, it may not be easy to erase and write data, and a general user may experience difficulties in updating memory contents. Contrarily, EEPROM may erase and write data electrically without difficulty and may become widely used in system programming for continuous updating and also auxiliary memory devices.
A flash EEPROM (hereinafter, referred to as a flash memory) may have a higher degree of integration compared to a conventional EEPROM, such that it may be advantageous for a high capacity auxiliary memory device. Among flash memories, a NAND flash memory may have a higher degree of integration than a NOR flash memory.
Flash memory may be classified into NOR flash memory and NAND flash memory depending on connection states between a cell and a bit line. Generally, because the NOR flash memory may have high power consumption, it may be disadvantageous for a high degree of integration, but it may be advantageous for a high speed operation. Additionally, since the NAND flash memory may consume a relatively small cell current, it may be advantageous for a high degree of integration.
Data in memory cells of a NAND flash memory may be erased and programmed through a Fowler-Nordheim tunneling current. On the other hand, a flash memory device may be programmed through an incremental step pulse programming (ISPP) scheme to accurately control threshold voltage distribution.
To store data in a memory cell array, a data load instruction may be given to a flash memory first, and then an address and data may be continuously inputted into the flash memory. Generally, data to be programmed may be sequentially transmitted to a page buffer by a byte or word unit. When all the data to be programmed, i.e., one page amount of data, are loaded in the page buffer, the stored data in the page buffer may be simultaneously programmed memory cells of a selected page in the memory cell array according to a program instruction. Generally, a cycle during which data may be programmed may be called a program cycle and may include a plurality of program loops, and each program loop may be divided into a program interval and a program verify interval.
During the program interval, memory cells may be programmed according to a well-known method under bias conditions. During the program verify interval, it may be verified whether memory cells are programmed up to a desired threshold voltage or not. The program loops may be repeatedly performed a predetermined number of times or until all the memory cells are programmed.
A program verify operation may be identical to a read operation except that read data may not be outputted to the outside. There are various suggested verifying methods that may determine whether memory cells are programmed up to a desired threshold voltage or not. One of the various verifying methods may be a wired-OR type.
A flash memory device may include a program state detection circuit. The program state detection circuit may simultaneously receive data stored in a latch of a page buffer and may detect whether the inputted data values represent program data values or not during a program verify interval. For example, the program state detection circuit may output a normal detect signal when all the selected memory cells are programmed to the optimized state, or may output an abnormal detect signal when at least one of the selected memory cells is insufficiently programmed.